1. Field of the Invention
The present invention relates to a method of designing an ESD protection circuit, in particular an ESD protection circuit for protecting semiconductor elements, semiconductor logic elements, and so on, and in particular to a method of determining its circuit configuration and the parameters of its circuit elements. The present invention also relates to a simulation method used in designing an ESD protection circuit.
2. Description of the Related Art
An increasing number of semiconductor devices have ESD protection circuits to protect their semiconductor memory elements, semiconductor logic circuits, and so on from ESD (electrostatic discharge). An example of a circuit used for ESD protection is shown in “High Holding Current SCRs (HHI-SCR) for Power ESD Protection and Latch-up Immune IC Operation” (EOS/ESD Symp., 1A. 3, 2002) by M. P. J. Mergens, C. C. Russ, K. G. Verhaege, J. Armer, P. C. Jozwiak, and R. Mohn.
The design of an ESD protection circuit is an iterated process in which immunity is tested through simulation, the design of the ESD protection circuit is altered according to the result, and the circuit with the altered design is simulated again. Performing simulations can reduce the number of prototypes, and shorten the time from start of development to finished product.
One example of a conventional simulation method is disclosed in Japanese Patent Application Publication No. 2004-79952. The simulation method described in Japanese Patent Application Publication No. 2004-79952 circuit-simulates the snapback characteristic of an electrostatic discharge protection element configured with a MOSFET in an equivalent circuit that uses a gate terminal to which a gate voltage is input and a bipolar transistor, and represents impact ionization with three current sources.
An accurate simulation accordingly requires the use of many parameters, so the simulation itself is time-consuming, leading to the problem that designing the ESD circuit is time-consuming. Performing a simulation with fewer parameters is less accurate, requiring an increased number of iterations of the evaluation of simulation faults, redesign of the circuit, and further simulation, leading again to the problem that designing the ESD circuit is time-consuming.